;*************************************************************************
;*** Handlers for ATMEGA 88 ***
.org 0				;0
rjmp RESET			; Reset Handler
.org	INT0addr	;1
rjmp H_EXT_INT0		; IRQ0 Handler
.org	INT1addr	;2
rjmp H_EXT_INT1		; IRQ1 Handler
.org	PCI0addr	;3
rjmp H_PCINT0			; PCINT0 Handler=Pin Change Interrupt Request 0
.org	PCI1addr	;4
rjmp H_PCINT1			; PCINT1 Handler
.org	PCI2addr	;5
rjmp H_PCINT2			; PCINT2 Handler
.org	WDTaddr		;6
rjmp H_WDT			; Watchdog Timer Handler
.org	OC2Aaddr	;7
rjmp H_TIM2_COMPA		; Timer2 Compare A Handler
.org	OC2Baddr	;8
rjmp H_TIM2_COMPB		; Timer2 Compare B Handler
.org	OVF2addr	;9
rjmp H_TIM2_OVF		; Timer2 Overflow Handler
.org	ICP1addr	;A
rjmp H_TIM1_CAPT		; Timer1 Capture Handler
.org	OC1Aaddr	;B
rjmp H_TIM1_COMPA		; Timer1 Compare A Handler
.org	OC1Baddr	;C
rjmp H_TIM1_COMPB		; Timer1 Compare B Handler
.org	OVF1addr	;D
rjmp H_TIM1_OVF		; Timer1 Overflow Handler
.org	OC0Aaddr	;E
rjmp H_TIM0_COMPA		; Timer0 Compare A Handler
.org	OC0Baddr	;F
rjmp H_TIM0_COMPB		; Timer0 Compare B Handler~
.org	OVF0addr	;10
rjmp H_TIM0_OVF		; Timer0 Overflow Handler
.org	SPIaddr		;11
rjmp H_SPI_STC		; SPI Transfer Complete Handler
.org	URXCaddr	;12
rjmp H_USART_RXC		; USART, RX Complete Handler
.org	UDREaddr	;13
rjmp H_USART_UDRE		; USART, UDR Empty Handler
.org	UTXCaddr	;14
rjmp H_USART_TXC		; USART, TX Complete Handler
.org	ADCCaddr	;15
rjmp H_ADC			; ADC Conversion Complete Handler
.org	ERDYaddr	;16
rjmp H_EE_RDY			; EEPROM Ready Handler
.org	ACIaddr		;17
rjmp H_ANA_COMP		; Analog Comparator Handler
.org	TWIaddr		;18
rjmp H_TWI			; 2-wire Serial Interface Handler
.org	SPMRaddr	;19
rjmp H_SPM_RDY		; Store Program Memory Ready Handler
; ***** END OF FILE ******************************************************